Intel RSD FPGA Information (Type 198)
Source: Intel® RSD Firmware Extension Specification Software v2.3.2 (document 337201-003US), section 3.9.
Declares a field-programmable gate array (FPGA) of the system: what it is, its hard processor subsystem (HPS), its high-speed serial interface (HSSI), where it is reached on PCIe, and the memory on its package. The structure is present only if the system has FPGAs.
| Offset | Version | Name | Length | Value | Description |
|---|---|---|---|---|---|
|
2.0+ |
Type |
|
|
FPGA Information indicator |
|
2.0+ |
Length |
|
Varies |
Length of the structure |
|
2.0+ |
Handle |
|
Varies |
|
|
2.0+ |
FPGA Index |
|
|
One-based index of the FPGA in the system |
|
2.0+ |
FPGA Type |
|
|
Kind of the FPGA, see FPGA types |
|
2.0+ |
FPGA Status |
|
|
Current state of the FPGA, see FPGA status |
|
2.0+ |
Socket Identifier |
|
|
Socket the FPGA is integrated into. Meaningful for an integrated FPGA only. |
|
2.0+ |
FPGA Vendor |
|
|
Vendor of the FPGA, as a name or, for a discrete FPGA, as the vendor identifier of its PCI configuration space |
|
2.0+ |
FPGA Family |
|
|
Family of the FPGA |
|
2.0+ |
FPGA Model |
|
|
Model of the FPGA |
|
2.0+ |
FPGA Bit Stream Version |
|
|
Version of the bit stream loaded into the FPGA |
|
2.0+ |
FPGA HPS Core Count |
|
|
Number of the cores of the hard processor subsystem, if the FPGA has one |
|
2.0+ |
— |
|
Varies |
Not defined by the specification, which goes on from the core count to the
next field at |
|
2.0+ |
FPGA HPS ISA |
|
|
Instruction set of the cores of the hard processor subsystem, see HPS instruction sets |
|
2.0+ |
FPGA HSSI Configuration |
|
|
What the high-speed serial interface of the FPGA is configured for, see HSSI configurations |
|
2.0+ |
FPGA HSSI Port Count |
|
|
Number of the ports of the high-speed serial interface, e.g. 4 for "4x10G" or 2 for "2x16 PCIe" |
|
2.0+ |
FPGA HSSI Port Speed |
|
|
Speed of a port of the high-speed serial interface, in Gbit/s, or its number of the lanes for PCIe, e.g. 10 for "2x10G" or 16 for "2x16 PCIe" |
|
2.0+ |
FPGA HSSI Side Band Configuration |
|
|
Side band the high-speed serial interface is configured through, e.g. "SPI", "I2C-0" or "SMBus" |
|
2.0+ |
FPGA Reconfiguration Slots |
|
|
Number of the partial reconfiguration (PR) slots of the FPGA |
|
2.0+ |
PCIe Slot Number |
|
|
Physical number of the slot connected to the PCIe port the FPGA is reached at |
|
2.0+ |
PCIe Bus Identifier |
|
|
PCI bus number the FPGA is reached at |
|
2.0+ |
PCIe Device Identifier |
|
|
PCI device number the FPGA is reached at |
|
2.0+ |
PCIe Function Identifier |
|
|
PCI function number the FPGA is reached at |
|
2.0+ |
Thermal Design Power |
|
|
Thermal design power of the FPGA, in milliwatts |
|
2.0+ |
On Package Memory Technology |
|
|
Technology of the memory on the package of the FPGA, see Memory technologies |
|
2.0+ |
On Package Memory Capacity |
|
|
Capacity of the memory on the package, in MB of 220 bytes each, the way the memory sizes of SMBIOS are given |
|
2.0+ |
On Package Memory Speed |
|
|
Speed of the memory on the package, in MHz |
1. Intel RSD FPGA — Types
| Hex Value | Dec Value | Meaning |
|---|---|---|
|
|
Integrated |
|
|
Discrete |
|
|
Discrete, with a system on chip (SoC) or a hard processor subsystem (HPS) |
2. Intel RSD FPGA — Status
| Hex Value | Dec Value | Meaning |
|---|---|---|
|
|
Disabled |
|
|
Enabled |
3. Intel RSD FPGA — HPS instruction sets
| Hex Value | Dec Value | Meaning |
|---|---|---|
|
|
x86 |
|
|
x86-64 |
|
|
IA-64 |
|
|
ARM A32 |
|
|
ARM A64 |
|
|
MIPS32 |
|
|
MIPS64 |
|
|
OEM-specific |
4. Intel RSD FPGA — HSSI configurations
| Hex Value | Dec Value | Meaning |
|---|---|---|
|
|
Networking |
|
|
PCIe |
|
|
Information not available. The other fields of the high-speed serial interface are to be ignored. |
5. Intel RSD FPGA — Memory technologies
| Hex Value | Dec Value | Meaning |
|---|---|---|
|
|
None, the FPGA has no memory attached |
|
|
Embedded DRAM (eDRAM) |
|
|
High Bandwidth Memory (HBM) |
|
|
High Bandwidth Memory of the second generation (HBM2) |